1. Field of the Invention
This invention is in the field of digital data processing systems in which the central processor of the system includes a plurality of execution units. Each of the execution units executes a different subset of the instructions constituting the repertoire of the processor. The execution units are independent of each other and act in parallel. More particularly, this invention relates to a collector in which the results of the execution of instructions by the execution units are received and stored in program order and in which a current copy of the program addressable registers of the central processor is maintained, which copy is available for recovering from faults.
2. Description of the Prior Art
Typically, in the prior art central processing systems, the processor includes circuits for producing the addresses of the instruction words, fetching the instruction from memory, preparing the addresses of operands, fetching the operands from memory, loading data into designated registers, excecuting the instruction and, when the results are produced, writing the results into memory or into program visible registers.
To increase the performance, i.e., throughput, of data processing systems, various modifications have been incorporated in central processing units. To reduce the time required to obtain operands and instructions, high-speed caches located in the processor have been provided. In order to speed up the systems, the systems are synchronized, i.e., a clock produces clock pulses which control each step of the operation of a central processing unit. In pipelined processors, the steps of preparing and fetching the instructions and the operands are overlapped to increase performance.
Because some instructions in a synchronous data processing system take many more clock periods than others, or much more time than others to execute, there is an imbalance in the time required to execute different instructions. One solution to this problem is to divide the processor into a plurality of execution units, where each execution unit will execute a subset of the instruction repertoire of the processor. Executing more than one instruction at a time by operating the execution units in parallel increases the throughput of the processor; however, if the processor is provided with multiple execution units which execute instructions in parallel, there is a need, or requirement, to make certain that the results of the execution of instructions by each of the execution units are assembled in program order so that the data that is written into memory and into the program visible registers is written in proper order. It is also necessary that there be readily available a current and correct copy of the contents of the program addressable registers to allow for precise handling of faults and interrupts, and to allow for recovering from hardware errors.